1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-068179, filed Mar. 24, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Regarding a method of the related art for manufacturing a semiconductor device, a groove is formed in an insulating film. Then, a seed layer is formed so as to cover an inner surface of the groove and an upper surface of the insulating film. Then, a plating film, which fills the groove, is formed over the insulating film by an electrolytic plating method. Then, unnecessary portions of the seed layer and the plating film, which are positioned higher in level than the upper surface of the insulating film, are removed by a CMP (Chemical Mechanical Polishing) method. Thus, a single-damascene wire, which is made of the plating film, is formed in the groove.
Regarding another method of a related art for manufacturing a semiconductor device, an opening, which includes a groove and a through hole, is formed in an insulating film. Then, a seed layer is formed so as to cover an inner surface of the opening. Then, a plating film, which fills the opening, is formed over the seed layer by an electrolytic plating method. Then, unnecessary portions of the seed layer and the plating film, which are positioned higher than the upper surface of the insulating film, are removed by a CMP (Chemical Mechanical Polishing) method. Thus, a dual-damascene wire, which is made of the plating film, is formed in the groove and the through hole.
Hereinafter, the above two methods of forming damascene wires are called damascene processes. In the damascene process, it is preferable that voids are not included in the plating film filling the groove and the through hole.
Japanese Patent Laid-Open Publication No. 2000-80496 discloses a method in which a plating process is carried out at a low current, for a short time, so as to form a first plating film, that fills a narrow groove and a through hole with a small diameter. Then, the plating process is carried out at a large current so as to form a second plating film that fills a through hole with a large diameter.
Japanese Patent Laid-Open Publication No. 2004-124262 discloses a method in which a low current is applied to the seed layer (preliminary energization) when part of the seed layer is etched with a plating solution, and therefore the seed layer becomes discontinuous. Then, a high current is applied to the seed layer to form a plating film that fills the groove.
Japanese Patent Laid-Open Publication No. 2006-111896 discloses a method in which a seed layer is formed so as to cover an inner surface of a through hole penetrating through a substrate. Then, a plating film, which fills only a lower portion of the through hole, is formed while a current density on the upper surface side of the substrate is smaller than that on the lower surface side of the substrate. Then, a plating film is formed so as to fill the through bole with use of a plating solution containing a plating inhibitor and a plating accelerator, while a current density on the upper surface side of the substrate is larger than that on the lower surface side of the substrate.
It is important in the damascene process to perform a polishing after the CMP process in order to prevent dishing or erosion. Japanese Patent Laid-Open Publication No. 2004-270028 discloses a method in which a current is applied only in a direction in which a plating film is grown. Then, a current is applied only in a direction opposite to the direction in which the plating film is grown. Then, a current is applied only in a direction in which the plating film is grown. Thus, protrusion of the plating film filling a minute groove can be prevented, thereby preventing dishing and erosion which occur after the CMP process.
However, according to the methods disclosed in Japanese Patent Laid-Open Publication No. 2000-80496, No. 2004-124262, and No. 2004-270028, when a groove with a wide width (in which a wire is formed) and an opening with a large area in plan view (in which a pad is formed) cannot be filled with a plating film after the second plating film formation process, a CMP process to be performed on the plating film thereafter causes dishing, erosion, or the like to occur in the plating film filling the groove and the opening.
Further, according to the method disclosed in Japanese Patent Laid-Open Publication No. 2004-124262, although voids can be prevented from being included in the seed layer, the groove is filled with the plating film formed by applying a high current to the seed layer (i.e., the plating film having the poor burying characteristics). For this reason, when the width of the groove is small, voids are included in the plating film filling the groove. Generally, voids are likely to be included in a plating film filling a groove and a through hole in which a dual damascene wire is formed.
Moreover, the method disclosed in Japanese Patent Laid-Open Publication No. 2006-111896 is applicable only to a through hole penetrating through a substrate, and therefore cannot be applied to the damascene process.